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[Program doc] UART_spec

Description: a UART model with FIFO buffer, design with verilog
Platform: | Size: 145408 | Author: quang | Hits:

[VHDL-FPGA-Verilog] uart_EP3C16_FIFO

Description: Verilog编写的串口RS232收发字符串程序,使用FIFO作为数据缓冲区,有效收发字符串长度为256字节,解决了利用串口调试工具与FPGA通讯只能收发单字节的问题.-Programs for uart/RS232, it can receive and transmit strings.
Platform: | Size: 6756352 | Author: 515666524 | Hits:

[VHDL-FPGA-Verilog] FifoAndTestbench

Description: 这是一个verilog编写的同步fifo和testbench的设计-It is a synchronous fifo and testbench design with verilog
Platform: | Size: 2048 | Author: 王强 | Hits:

[VHDL-FPGA-Verilog] Verilog_CY7C68013-SLAVE-FIFO

Description: 用VERILOG 编写 CY7C68013 usb数据采集SLAVE FIFO模式驱动程序 ，已验证过-Prepared with the VERILOG CY7C68013 usb data acquisition SLAVE FIFO mode driver, has proven
Platform: | Size: 667648 | Author: 高亮 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 运用Verilog 语言对FPGA实现同步的FIFO的数据缓存和传输功能。-FPGA Verilog language used to synchronize the FIFO data buffer and transmission functions.
Platform: | Size: 432128 | Author: 张伟 | Hits:

[VHDL-FPGA-Verilog] fifo_tb

Description: verilog implementation of 16X4 fifo with testbench
Platform: | Size: 1024 | Author: prateek | Hits:

[VHDL-FPGA-Verilog] FIFO-verilog

Description: 本实验完成的是8位异步FIFO的设计，其中写时钟100MHz,读时钟为5MHz，其中RAM的深度为256。当写时钟脉冲上升沿到来时，判断写信号是有效，则写一个八位数据到RAM中；当读时钟脉冲上升沿到来时，判断读信号是有效，则从RAM中把一个八位数据读出来。当RAM中数据写满时产生一个满标志，不能再往RAM再写数据；当RAM中数据读空时产生一个空标志，不能再从RAM读出数据。-In this study, completed the 8-bit asynchronous FIFO design, which write clock 100MHz, read clock is 5MHz, the depth of the RAM 256. When the rising edge of write clock pulse when writing the signal is valid, then write an eight-bit data to RAM when the rising edge of read clock pulse, the judge read the signal is valid, from eight bits of data in RAM to a read out. When RAM is full of data to generate a full mark, can not go down RAM write data when the RAM data read empty an empty sign, can not read data from RAM.
Platform: | Size: 333824 | Author: 肖波 | Hits:

[VHDL-FPGA-Verilog] FIFO-verilog

Description: 两种异步FIFO设计以及源代码（Verilog）-Two asynchronous FIFO design and source code (Verilog)
Platform: | Size: 12288 | Author: 范先龙 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 异步FIFO Verilog源代码，对控制读写地址进行设计，以便写满和读空只产生一个标志，实现对FIFO的缓冲控制-Asynchronous FIFO Verilog source code, designed to control read and write addresses in order to fill and read empty produce only one flag, the FIFO buffer control
Platform: | Size: 3072 | Author: zx | Hits:

[VHDL-FPGA-Verilog] fifo

Description: 利用verilog来实现fifo的读写，并有testbench程序。-fifo verilog
Platform: | Size: 1024 | Author: meihanfei | Hits:

[VHDL-FPGA-Verilog] fifo-verilog

Description: 用verilog 编写的fifo（先入先出队列）代码 内含测试文件 test bench-First Input First Output programme which designed by verilog codes,including test bench
Platform: | Size: 1024 | Author: 贺铮 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 用verilog编写FIFO，并编写了相应的测试向量-Write FIFO Verilog
Platform: | Size: 525312 | Author: 郝继龙 | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: Verilog HDL语言编写异步FIFO-Verilog HDL language, asynchronous FIFO
Platform: | Size: 3072 | Author: 赵鑫 | Hits:

[File Format] FIFO

Description: FIFO verilog VHDL-FIFO verilog VHDL
Platform: | Size: 52224 | Author: 徐云川 | Hits:

[Other] fifo

Description: 同步fifo的verilog代码，很好的资料，值得学习-Synchronous fifo verilog code, very good information, it is worth learning
Platform: | Size: 1024 | Author: 李军 | Hits:

[Other] fifo

Description: 异步fifo ,verilog 源代码，含工程文件，modosim 下运行-Asynchronous fifo verilog source code containing the project file run modosim
Platform: | Size: 175104 | Author: zhaoyibin | Hits:

[VHDL-FPGA-Verilog] asynchronous-FIFO-verilog

Description: FIFO是英文First In First Out 的缩写，是一种先进先出的数据缓存器，他与普通存储器的区别是没有外部读写地址线，这样使用起来非常简单-FIFO is an abbreviation of the English First In First Out, is a first-in, first-out data buffer, the difference between him and ordinary memory is external read and write address lines, very simple to use
Platform: | Size: 14336 | Author: chenkun | Hits:

[VHDL-FPGA-Verilog] FIFO

Description: 三种同步方式实现的FIFO，verilog HDL，FPGA，更好理解FIFO-The three implemented synchronously FIFO, Verilog HDL, FPGA, a better understanding of the FIFO
Platform: | Size: 8192 | Author: fan | Hits:

[VHDL-FPGA-Verilog] synchronous-FIFO

Description: 同步fifo的使用verilog案例讲解-The use of synchronous fifo verilog case to explain
Platform: | Size: 265216 | Author: Ande | Hits:

[VHDL-FPGA-Verilog] async_fifo-and-verilog

Description: 异步fifo的详细原理分析说明及verilog源代码，经典推荐！-Detailed description of the principles and analysis of asynchronous fifo verilog source code, the classic recommendation!
Platform: | Size: 12288 | Author: 雨茗 | Hits:
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